This invention relates to semiconductor memory devices, memory chips, memory modules, and memory controllers.
Because of the physical structure, a memory cell array is organized as a large number of rows by a large number of columns. The maximum potential width for parallel data transfer equals the number of columns times the number of bit planes. For a 64 mega-bit memory chip organized as 8192 rows, 1024 columns, and 8 bits, the maximum data width is 8192 bits.
However, due to the pin count limitation of semiconductor chips and modules, the actual data transfer width is set to be a much smaller number. The data input-output width for a memory chip is typically 1, 2, 4, 8, or 16 bits.
Internally, many columns of a memory cell array are multiplexed together to form a memory input-output data bit line. In doing so, the speed of memory data transfer is limited to the width and frequency of the memory data line.
For a memory chip with an 8192-row 1024-column 8-bit cell array, the 1024 columns are multiplexed into a 1-bit memory data line. The data width of the memory array is reduced by a factor of 1024.
As the density of the semiconductor memory device increases, the size of the memory cell array increases as well. The data width reduction factor also becomes larger.
The system functionality demands high-speed processing of a large amount of memory data. As the speed of the processing unit increases to a higher level, the limitation in memory data transfer rate becomes a severe speed bottleneck for a processing system.